1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional printed memory (3D-P).
2. Prior Arts
Three-dimensional printed memory (3D-P), also known as three-dimensional mask-programmed read-only memory (3D-MPROM), is a monolithic semiconductor memory comprising a plurality of vertically stacked memory levels. U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-P (3D-MPROM). It comprises a substrate level OK and a plurality of vertically stacked memory levels 10, 20 (FIG. 1A). The substrate level OK comprises decoders 14, 24 for the memory levels 10, 20. It is covered by a planarized insulating dielectric 0d. A first memory level 10 is stacked above the insulating dielectric 0d, and a second memory level 20 is stacked above the first memory level 10. The first memory level 10 is coupled to the substrate circuit OK through contact vias 13a, while the second memory level 20 is coupled to the substrate circuit OK through contact vias 23a. 
Each of the memory levels (e.g. 10, 20) comprises at least a memory array (e.g. 100A, 200A). Each memory array (e.g. 100A) comprises a plurality of upper address-select lines (i.e. y-lines, e.g. 12a-12d, 22a-22d), lower address-select lines (i.e. x-lines, e.g. 11a, 21a) and memory devices (e.g. 1aa-1ad, 2aa-2ad) at the intersections between the upper and lower address lines. A memory array 100A is a collection of memory devices (e.g. 1aa-1ad, 2aa-2ad) in a memory level 10 that share at least one address-select line (e.g. 11a, 12a-12d). Within a memory array (e.g. 100A), all address-select lines (e.g. 11a, 12a-12d) are continuous; between adjacent memory arrays, address-select lines are not continuous.
A 3D-P die 1000 comprises a plurality of the memory blocks (e.g. 1aa, 1ab . . . 1dd) (FIG. 1B). The structure shown in FIG. 1A is part of the memory block 1aa. A memory block 1aa is a portion of the 3D-P die 100 whose topmost memory level 20 comprises only a single memory array 200A. Within the topmost memory level 20 of the memory block 1aa, all address-select lines 21a, 22a-22d are continuous and terminate at or near the edge of the memory block 1aa. In prior-art 3D-P, all memory blocks (e.g. 1aa-1dd) in a 3D-P die 1000 have the same size; and, within each memory block 100, the memory arrays (e.g. 100A, 200A) in all memory levels (e.g. 10, 20) have the same size.
As the storage capacity of a 3D-P increases (a single 3D-P die can store up to 1 Tb), more contents can be stored therein, including slow contents that do not require fast access (e.g., digital books, digital maps, music, movies, and/or videos) and fast contents that require fast access (e.g., operating systems, software, and/or games). Prior arts integrate these contents into a single 3D-P die with memory blocks and memory arrays of same sizes. This causes several problems. If the memory array is made too small, poor array efficiency leads to a higher die cost. On the other hand, if the memory array is made too large, slow memory speed may not meet the speed requirement of fast contents.